GPU Kernel Optimization Develop and optimize low level GPU kernels to accelerate inference and training of large machine learning models. Maximize the computational efficiency and reduce execution time while ensuring model accuracy. Multi GPU and Multi Node Optimization Design and implement strategies for distributed model training and inference across multiple GPUs and n

Define, plan, and drive engineering program plans based on senior technical guidanceand involving multi component environment (AMD IPs, SOCs, HW, SW, FW) Provide program management leadership to technical teams spanning multiple disciplines/geographies. Craft, lead, and continually improve program level processes and methodologies. Identify and manage program dependencies

Collaborate with architects, hardware engineers, and firmware engineers to understand the new power features to be verified Coordinate between RTL Power team and Verification teams to drive workload/test vectors readiness for power estimation Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD

High Speed PCB Design development Develop routing strategies for new IP including, PCIe, DP, Memory, XGMI Stackup creation and high speed material selection. Strategizing with a variety of teams including, SI, EMI, PI, Thermal and Mechanical Development of Design rules Aiding in the development of New Tools and Processes Developing ASIC ball outs Experience in memory, HDI

Lead an x86 Core DV engineering team. Build a team and nurture talent. Lead the team, participate in technical discussions, meet schedule commitments, and provide strong support to customers. Collaborate with multi functional leaders, such as RTL, Physical Design, and Performance team leaders, to drive AMD's success. PREFERRED EXPERIENCE A strong leader with experience wo

RTL design for memory I/O PHY Digital Architecture development from pathfinding, coding, verification to physical implementation PHY link layer design, implementation & verification with Analog and System architect. PHY Analog/Digital co design Digital design and RTL coding Timing Synthesis & Drive Physical implementation Collaborate with architects, hardware engineers, a

Lead post silicon performance characterization, validation and optimization Communicate, propose, and implement solutions to processor and system performance issues using an in depth design architecture and micro architecture understanding. Collaborate in micro benchmarking, workload characterization, competitive analysis, bottleneck identification, and optimization. Deve

Collaborate with design, validation, and architecture teams for content coverage, test pattern development, validation, and debugging Develop test program infrastructure incorporating latest Best Known methods Solves sophisticated, novel, and non recurring problems; initiates significant changes to existing processes/ methods and leads development and implementation Ident

Developing new flow features around new EDA tools and tool capabilities. Developing innovative physical design place & route methodology and flow solutions to meet current and future digital design challenges. Working closely with EDA vendors to evaluate their capabilities and drive future improvements to meet AMD roadmap requirements. Tuning the design flows to achieve o

Proficiency in Machine Learning techniques and its application Proficiency in 3D graphics and Ray tracing using GPU Compute and Graphics APIs like Direct3D, Vulkan, OpenGL, OpenCL, CUDA Ability to program in low level languages (x86 asm, SSE, ISA) General software development workflow knowledge git, cmake, CI, etc Expert programming skills in C and/or C++ Proven successfu

Work closely with Infinity Fabric architects, micro architects, performance and DV teams to understand new features, arrive at efficient routing configurations, finalize settings, and formulate new silicon test requirements. Engage with product, platform, and diagnostic development teams to describe and ensure stressing of all new or important design features. Engage with

Define performance suite and best practices for measuring GPU accelerated workloads to assess scalability and efficiency of AI models and algorithms Benchmark and analyze AI workloads in single and multi node configurations comparing against previous generations and our competitors Perform comprehensive performance analysis and report findings for the entire platform incl

Responsible for analyzing and optimizing workloads running on AMD based hardware in the cloud computing environments of our key partners. This analysis spans the full stack including the application and related frameworks, the Java Virtual Machine, operating system (Linux and Windows Server), hypervisor, network and storage drivers, BIOS, CPU core, memory & I/O subsystems

Responsible for specifying next generation architecture definition Especially in areas of data movement and reshaping, synchronization, control and reconfiguration, interfacing with SoC, security and reliability, debug and trace. Performance modelling and specifying performance requirements Specification of solutions (spoken, written & figures) Understanding key use cases